library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity decode is
port(cntin1:in std_logic_vector(3 downto 0);cntin2:in std_logic_vector(3 downto 0);ledout1:out std_logic_vector(6 downto 0);ledout2:out std_logic_vector(6 downto 0));
end entity decode;

architecture behav of decode is
begin 
	with cntin1 select 
		ledout1 <= "1111110" when "0000",
						"0110000" when "0001",
						"1101101" when "0010",
						"1111001" when "0011",
						"0110011" when "0100",
						"1011011" when "0101",
						"1011111" when "0110",
						"1110000" when "0111",
						"1111111" when "1000",
						"1111011" when "1001",
						"1001111" when others;

	with cntin2 select 
		ledout2 <= "1111110" when "0000",
						"0110000" when "0001",
						"1101101" when "0010",
						"1111001" when "0011",
						"0110011" when "0100",
						"1011011" when "0101",
						"1011111" when "0110",
						"1110000" when "0111",
						"1111111" when "1000",
						"1111011" when "1001",
						"1001111" when others;
end architecture behav;




